This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-022160, filed Jan. 30, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a digital-to-analog converter and a synchronous circuit using the converter. More specifically, the present invention relates to an analog DLL (delayed locked loop) provided in a DRAM (dynamic random access memory).
2. Description of the Related Art
A prior art DRAM includes an analog DLL using a digital-to-analog converter. The analog DLL is provided in order to make the rising timing of an input clock signal and that of an output clock signal coincident with each other.
FIG. 10 shows an example of a configuration of the above-described analog DLL. In FIG. 10, a DAC (digital-to-analog converter) 1 converts a digital signal (bit n(nx)) to a current amount (analog signal nout). The digital signal (bit n(nx)) is supplied from a bit controller 5 serving as a generation circuit. The DAC 1 sends the analog signal nout to a delay line 2. In accordance with the current amount, an operation of a delay unit (not shown) that is a unit delay element for control of current is controlled. Thus, the delay line 2 varies an amount of delay between a reference signal rclk and an output signal iclk.
A replica circuit 3 generates a delay signal dclk from the output signal iclk of the delay line 2 and supplies the delay signal dclk to a phase detector 4. The phase detector 4 compares the phases of the delay signal dclk and reference signal rclk to obtain a phase difference signal px and supplies the signal px to the bit controller 5. The bit controller 5 converts the phase difference signal px to the digital signal (bit n(nx)).
In the analog DLL so configured, a parallel-variable-resistance type DAC is commonly used. This type of DAC comprises a digital voltage converter 101, a differential amplifier 102, and a current generation circuit 103, as illustrated in FIG. 11.
The digital voltage converter 101 includes a constant-current source 101a and a parallel variable resistor 101b. The parallel variable resistor 101b has a resistor R0 and a plurality of resistors r0/n arranged in parallel with the resistor R0 (In FIG. 11, a plurality of resistors r0 are shown as a composite one r0/n for the sake of convenience). The digital voltage converter 101 controls a resistance value of the parallel variable resistor 101b in response to the digital signal (bit n(nx)). The number n of resistors r0 connected to the resistor R0 is changed. Thus, the digital voltage converter 101 freely varies a generated potential Vx in response to the digital signal (bit n(nx)). The potential Vx is expressed by the following equation:
Vx=(I0)*(R0*r0/n)/(R0+r0/n)
The differential amplifier 102 includes a current-mirror type operational amplifier 102a, a PMOS transistor (channel width Wa) 102b, and a resistor R. The digital voltage converter 101 applies the potential Vx to an inverting input (xe2x88x92) terminal of the operational amplifier 102a. The gate of the PMOS transistor 102b is connected to the output terminal of the operational amplifier 102a. The drain of the PMOS transistor 102b is connected to a noninverting input (+) terminal of the operational amplifier 102a. The resistor R is connected to the drain of the PMOS transistor 102b. In other words, the differential amplifier 102 controls current Ix flowing through the resistor R such that the potential Vx at the inverting input terminal of the operational amplifier 102a and the potential Vy at the noninverting input terminal thereof become equal to each other.
The current generation circuit 103 includes a PMOS transistor (channel width Wb) 103a and an NMOS transistor 103b. The PMOS transistor 103a is mirror-connected to the PMOS transistor 102b. The gate and drain of the NMOS transistor 103b are connected to the drain of the PMOS transistor 103a. In other words, the current generation circuit 103 mirrors the current Ix based on the ratio of channel width Wa of the PMOS transistor 102b to channel width Wb of the PMOS transistor 103a. Thus, the circuit 103 generates a current (analog signal nout) I in response to the output (current Ix) of the differential amplifier 102. The current I is given by the following equation:
I=(Vx/R)*(Wb/Wa)
In the analog DLL described above, the DAC 1 varies the amount of current I supplied to the delay line 2 in response to the digital signal (bit n(nx)). Then, the DAC 1 changes the amount of delay on the delay line 2 in accordance with the amount of current I. The reference signal rclk and the output signal iclk are therefore synchronized with each other.
In the parallel variable resistance type DAC, however, the amount of current I cannot completely be changed freely in response to the digital signal (bit n(nx)) since the above DAC has the following two constraints.
The first constraint is concerned with an input voltage (potential Vx at the inverting input terminal) of the current-mirror type operational amplifier 102a. The potential Vx should be one capable of stably operating a current mirror. When a power supply level is set at 1.8V, the potential necessary for stably operating the current mirror ranges from about 0.5V to 1.5V. The amount of variation xcex94I in current I supplied to the delay line 2 thus depends upon the amount of change of potential Vx. The variation amount xcex94I depends upon the operating range of the current mirror.
The second constraint is concerned with a high frequency. For synchronization with a high-frequency clock signal, a certain amount of current has to flow because the delay line 2 varies the rising/falling speed of pulse in accordance with the amount of current I to be supplied. The delay amount is changed accordingly. If the current flowing through the high-frequency clock signal is too small, pulses will disappear. The disappearance of pulses makes synchronization with the clock signal impossible.
Under the above constraints, the variation amount xcex94I of current I is fixed almost uniquely. If the variation amount xcex94I in the DAC 1 is fixed, the amount of delay caused by the delay line 2 is done. In order to vary the amount of delay, the number of delay elements has only to be changed. Therefore, a number of delay elements are required in order to broaden the frequency range of a clock signal for synchronization.
A digital-to-analog converter circuit according to a first aspect of the present invention comprises a converter configured to convert digital signals of bit n (n=0, 1, 2, . . . , N) to voltage values, a plurality of amplifiers configured to output currents having different values in accordance with the voltage values, and an adder configured to assigning weights to the currents and adding the currents together in response to the digital signal of bit n.
A synchronous circuit according to a second aspect of the present invention comprises a digital-to-analog converter circuit including a converter configured to convert digital signals of bit n (n=0, 1, 2, . . . , N) to voltage values, a plurality of amplifiers configured to output currents having different values in accordance with the voltage values obtained by the converter, and an adder configured to assign weights to the currents and add the currents together in response to the digital signals of bit n, a delay line including a unit delay element that receives an output from the digital-to-analog converter circuit and varies in delay amount according to the output, a phase detector configured to compare an output of the delay line and a phase of a reference signal with each other, and a generator configured to generate the digital signal of bit n in response to an output of the phase detector.
A synchronous circuit according to a third aspect of the present invention comprises a digital-to-analog converter circuit including a converter configured to convert digital signals of bit n (n=0, 1, 2, . . . , N) to voltage values, a plurality of amplifiers configured to output currents having different values in accordance with the voltage values obtained by the converter, and an adder configured to assign weights to the currents and add the currents together in response to the digital signals of bit n, the adder having a common node supplied with the added currents and connected to a gate and a drain of a transistor, a delay line including a unit delay element that receives an output from the digital-to-analog converter circuit and varies in delay amount according to the output, a phase detector configured to compare an output of the delay line and a phase of a reference signal with each other, and a generator configured to generate the digital signal of bit n in response to an output of the phase detector.